Packet classification has become a key processing function to enable future flow-based networking schemes. As network capacity\nincreases and new services are deployed, both high throughput and reconfigurability are required for packet classification\narchitectures. FPGA technology can provide the best trade-off among them. However, to date, lookup stages have been mostly\ndeveloped as independent schemes from the classification stage, which makes their efficient integration on FPGAs difficult. In\nthis context, we propose a new interpretation of the lookup problem in the general context of packet classification, which enables\ncomparing existing lookup schemes on a common basis. From this analysis, we recognize new opportunities for optimization of\nlookup schemes and their associated classification schemes on FPGA. In particular, we focus on the most appropriate candidate for\nfuture networking needs and propose optimizations for it. To validate our analysis, we provide estimation and implementation\nresults for typical lookup architectures on FPGA and observe their convenience for different lookup and classification cases,\ndemonstrating the benefits of our proposed optimization.
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